The present invention relates in general to apparatus for verifying electronic circuit designs and more specifically to hardware emulation systems in which multiple design signals are carried on a single physical wire between programmable logic chips.
Hardware emulation systems are devices designed for verifying electronic circuit designs prior to fabrication as chins or printed circuit boards. These systems are typically built from programmable logic chips (logic chips) and programmable interconnect chips (interconnect chips). The term. xe2x80x9cchipxe2x80x9d as used herein refers to integrated circuits. Examples of logic chips include reprogrammable logic circuits such as field-programmable gate arrays (xe2x80x9cFPGAsxe2x80x9d), which include both off-the-shelf products and custom products. Examples of interconnect chips include reprogrammable FPGAs, multiplexer chips, crosspoint switch chips, and the like. Interconnect chips can be either off-the-shelf products or custom designed.
Prior art emulation systems have generally been designed so that each signal in an electronic circuit design to be emulated is mapped to one or more physical metal lines (xe2x80x9cwiresxe2x80x9d) within a logic chip. Signals which must go between logic chips are mapped to one or more physical pins on a logic chip and one or more physical traces on printed circuit boards which contain the logic and interconnect chips.
The one-to-one mapping of design signals to physical pins and traces in prior art emulation systems leads to the requirement that the emulation system contain at least as many logic chip pins and printed circuit board traces as there are design signals to be routed between logic chips. Such an arrangement requires the use of very complex and expensive integrated circuit packages, printed circuit boards and circuit board connectors to construct the emulation system. The high cost of these components, an which in rum increases the cost of the hardware logic emulation system, is a factor in limiting the number of designers who can afford, and therefore, benefit from, the advantages provided by hardware emulation systems.
Furthermore, integrated circuit fabrication technology is allowing the use of ever decreasing feature sizes. Thus, the logic density of logic chips (i.e., the number of logic gates that can be implemented therein) has increased dramatically. The increase in the number of logic gates can be implemented or emulated in a single logic chip, however, has not been met with an increase in the number of pins (i.e., leads) available for inputs, outputs, clocks and the like on the chip""s package. The number of pins on an integrated circuit package is limited by the available perimeter of the chip. Furthermore, the capability of the wire-bonding assembly equipment used to connect the bonding pads on integrated circuit dice to the pins on the package has increased slowly over time. Thus, there is an increasing mismatch between the amount of logic available on a logic chip and the number of pins available to connect the logic to the outside world. This results in poor average utilization of the logical capacity of the logic chips, which increases the cost of a hardware emulation system necessary for emulation of a given sized electronic circuit design.
Time-multiplexing is a technique that has been used for sharing a single physical afire or pin between multiple logical signals in certain types of systems where the cost of each physical connection is very high. Such systems include telecommunication systems. Time-multiplexing, however, has not been commonly used in hardware emulation systems such as those available from Quickturn Design Systems, Inc., Mentor Graphics Corporation, Aptix Corporation, and others because the use of prior art time-multiplexing methods significantly reduced the speed at which the emulated circuit could operate. Furthermore, prior art time-multiplexing techniques makes it difficult to preserve the correct asynchronous behavior of an embedded design in the hardware emulation system.
As discussed, one function of hardware emulation systems is to verify the functionality of an integrated circuit. Typically, when a circuit designer or engineer designs an integrated circuit, the design is represented in the form of a xe2x80x9cnetlistxe2x80x9d description of the design. A netlist description (or xe2x80x9cnetlistxe2x80x9d, as it is referred to by those of ordinary skill in the art) is a description of the integrated circuit""s components and electrical interconnections between the components. The components include all those circuit elements necessary for implementing a logic circuit, such as combinational logic (e.g., gates) and sequential logic (e.g., flip-flops and latches). Prior art emulation systems analyzed the user""s circuit netlist prior to implementing the netlist into the hardware emulation system. This analysis included the steps of separating the various circuit paths of the design into clock paths, clock qualifiers and data paths. A method for performing this analysis and separation is disclosed in U.S. Pat. No. 5,475,830 by Chen et al. which is assigned to the same assignee as the present invention. The disclosure of U.S. Pat. No. 5,475,830 is incorporated herein by reference in its entirety. The techniques disclosed in U.S. Pat. No. 5,475,830 have been used in prior art emulation systems such as the System Realizer(trademark) brand hardware emulation system from Quickturn Design Systems, Inc., Mountain View, Calif. However, the techniques disclosed therein have not been used in combination with any type of time-multiplexing.
Other prior art hardware emulation systems such as those available from Virtual Machine Works (now IKOS), APKOS (now Synopsis) and IBM have attempted to use time-multiplexing of design signals onto a single physical logic chip pin and printed circuit board trace to seek lower hardware cost for a given size of electronic design to be emulated. These prior art emulation systems, however, alter or re-synthesize clock paths in an attempt to maintain correct circuit behavior. This alteration or re-synthesis process works predictably for synchronous design. However, altering or re-synthesizing the clock paths in an asynchronous design can lead to inaccurate or misleading emulation results. Since most circuit designs have asynchronous clock architectures, the need to alter or re-synthesize the clock paths is a large disadvantage.
In addition, prior art hardware emulation machines using time-multiplexing have suffered from low operating speed. This is a consequence of re-synthesizing the clock paths. In these machines, a number of internal machine cycles are required to emulate one clock cycle of a design. Thus, the effective operating speed for the emulated design is typically many times slower than the maximum clock rate of the emulation system itself. If there are multiple asynchronous clocks in the design to be emulated, the slowdown typically becomes even worse because of the need to evaluate the state of the emulated design between each pair of input clock edges.
Prior art hardware emulation machines using time-multiplexing also require complex software for synchronizing the flow of many design signals over a single physical logic chip pin or printed circuit board trace. Each design signal must be timed so that it has the correct value at the instant it is needed in other parts of the system to compute other design signals. This timing analysis software (also known as scheduling software) adds to the complexity of the emulator and to the time needed to compile a circuit design into the emulator.
Furthermore, prior art hardware emulation machines which use time-multiplexing only use a simple form of time-multiplexing which requires minimal hardware but uses a large amount of power (e.g., current) and requires a complex system design.
Thus, there is a need for a hardware emulation system which has very high logical capacity, fast compile times, less complex software, simplified mechanical design and reduced power consumption.
A near type of hardware emulation system is disclosed and claimed which reduces hardware cost by time-multiplexing multiple design signals onto physical logic chip pins and printed circuit board traces but which does not have the limitations of low operating speed and poor asynchronous performance. Additional methods to multiplex multiple signals onto a single physical interconnection which are suitable for hardware emulation but do not have the disadvantages of high power and complex system design are also disclosed.
In the preferred embodiment, time-multiplexing is performed on clock qualifier paths (a clock qualifier is any signal which is used to gate a clock signal) and data paths in a design but not on clock paths (a clock path is the path between the clock signal and the clock source from which the clock signal is derived).
The reconfigurable logic system of the present invention comprises a plurality of reprogrammable logic devices, each having internal circuitry which can be reprogrammably configured to provide at least combinatorial logic elements and storage elements. The programable logic devices also have programable input/output terminals which can be reprogrammably interconnected to selected ones of functional elements of the logic devices. The reprogrammable logic devices have input demultiplexers and output multiplexers implemented at each input/output terminal. The input demultiplexers receive a time-multiplexed signal and divide it into one or more internal signals. The output multiplexers combine one or more internal signals onto a single physical interconnection.
The invention also comprises a plurality of reprogrammable interconnect devices, each of which have input/output terminals and internal circuitry which can be reprogrammably configured to provide interconnections between selected input/output terminals. The reprogrammable interconnect devices also have input demultiplexers and output multiplexers implemented at each input/output terminal. The input demultiplexers receive a time-multiplexed input signal and divide it into one or more component signals. The output multiplexers combine one or more component signals onto a second single physical interconnection.
The invention also comprises a set of fixed electrical conductors connecting the programmable input/output terminals on the reprogrammable logic devices to the input/output terminals on the reprogrammable interconnect devices.
In another aspect of the present invention, a logic analyzer is integrated into the logic emulation system which provides complete visibility of the design undergoing emulation. The logic analyzer of the present invention is distributed, in that its components are integrated into many of the resources of the emulation system. The logic analyzer of the present invention comprises having at least scan chains programmed into each of the logic chips of the logic boards. The scan chains are comprised of at least one flip-flop. The scan chains are programmably connectable to selected subsets of sequential logic elements of the design undergoing emulation.
The logic analyzer further comprises at least one memory device which is in communication with the scan chain. This memory device stores data from the sequential logic elements of the logic design undergoing emulation. Control circuitry communicates with the logic chips of the emulation system and generates logic analyzer clock signals which clock the scan chains. The control circuitry also generates trigger signals when predetermined combination of signals occur in the logic chips.
The above and other preferred features of the invention, including various novel details of implementation and combination of elements will now be more particularly described with reference to the accompanying drawings and pointed out in the claims. It will be understood that the particular methods and circuits embodying the invention are shown by way of illustration only and not as limitations of the invention. As will be understood by those skilled in the art, the principles and features of this invention may be employed in various and numerous embodiments without departing from the scope of the invention.